1. Field of the Invention
The present invention relates to a metal-oxide-semiconductor (MOS) device process and, more particularly, to a MOS device with dual gate insulators and a method of forming the same.
2. Description of the Related Art
In highly integrated VLSI or ULSI processing, high-voltage (HV) MOS devices and low-voltage (LV) MOS devices are formed within the active areas and HV I/O devices are formed in the peripheral circuit areas. Since the HV MOS device has a longer channel length and a thicker gate insulator in comparison with the LV MOS device, how to provide two gate insulators of different thickness becomes an important problem to be solved.
FIGS. 1A to 1E are sectional diagrams showing a method of forming HV MOS devices and LV MOS devices according to the prior art. As shown in FIG. 1A, a semiconductor substrate 10 has a plurality of shallow trench isolation regions 12 for separating adjacent active areas, such as a HV MOS device region I and a LV MOS device region II. As shown in FIG. 1B, a first oxide layer 14 is formed on the entire surface of the substrate 10, and then photolithography and etching are employed to remove the first gate oxide layer 14 within the LV MOS device region II, thus the first oxide layer 14 only remains on the HV MOS device region I. Next, a second oxide layer 16 is formed on the entire surface of the substrate 10 to cover the first oxide layer 14 and the exposed area of the substrate 10. Therefore, the stacked structure consisting of the first oxide layer 14 and the second oxide layer 16 within the HV MOS device region I serves as a thick gate oxide insulator of the HV MOS device. Also, the second oxide layer 16 within the LV MOS device region II serves as a thin gate oxide insulator of the LV MOS device. Thereafter, as shown in FIG. 1C, after depositing a polysilicon layer on the substrate 10, photolithography and etching are employed to pattern the polysilicon layer as a first gate electrode layer 18 in the HV MOS device region I and a second gate electrode layer 20 in the LV MOS device region II.
As the channel length is scaling down, hot-carrier effect has indeed become a significant problem in NMOS devices, especially when the channel length is smaller than 1.5 xcexcm. Lightly doped drains (LDD) structure is one way to solve this problem. As shown in FIG. 1D, using lightly-doped ion implantation with the gate electrode layers 18 and 20 as the mask, a lightly-doped region 22 is formed in the substrate 10 and surrounds the gate electrode layers 18 and 20. Then, as shown in FIG. 1E, using deposit, photolithography and anisotropic etching, a sidewall spacer 24 is formed on the sidewalls of the gate electrode layers 18 and 20. Next, using heavily-doped ion implantation with the gate electrode layers 18 and 20 and the sidewall spacer 24 as the mask, a heavily doped region 26 is formed in the exposed area of the lightly doped region 22 to serve as a source/drain electrode region. The remaining lightly doped region 22 serves as an LDD structure. Thus, the HV MOS device completed within the HV MOS device region I has a channel length dI longer than a channel length dII of the LV MOS device completed within the LV MOS device region II.
The present invention provides a MOS device with dual gate insulators and a method of forming the same to solve the problems mentioned in the prior art.
The MOS device with dual gate insulators has a first gate insulator formed on a predetermined area of a semiconductor substrate, and a second gate insulator formed outside the predetermined area of the semiconductor substrate to surround the first gate insulator. The second gate insulator is thicker than the first gate insulator. In addition, a gate electrode layer is patterned on the dual gate insulators. The bottom center of the gate electrode layer covers the first gate insulator, and the bottom edge of the gate electrode layer extends to cover the second gate insulator.
Accordingly, it is a principal object of the invention to increases the channel length of the MOS device.
It is another object of the invention to improve the lateral electric field near the drain junction.
Yet another object of the invention is to improve the vertical electric field near the drain junction.
It is a further object of the invention to diminish a parasitic capacitance at the bottom corner of the gate electrode.
Still another object of the invention is to overcome hot-carrier effect without fabricating an LDD structure.
Another object of the invention is to reduce process time and costs.
These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings.